The present invention relates to multi-ported memory devices, device layouts and processes for fabricating such devices.
Development of semiconductor memory devices has been increasing at a fast pace in recent times because of major breakthroughs in materials, manufacturing processes and designs of semiconductor devices. Semiconductor device manufacturers are constantly enhancing their efforts for more advanced miniaturization, high-integration and capacity increase of the semiconductor devices. As discussed in commonly owned U.S. Pat. Nos. 7,285,982; 7,285,981; 7,268,580; 6,998,722; 6,856,030; 6,849,958; and 6,828,689, all invented by the inventor of the present invention, the content of which is incorporated by reference, a latch is a data storage unit in a semiconductor device comprising of two inverters. An inverter has an input and an output having a voltage of opposite polarity to said input. The inverter is connected between a system power voltage level and system ground voltage level. Two such inverters connected back-to-back have self sustaining voltages at their inputs and outputs. A static random access memory (SRAM) device is a type of semiconductor memory device that has low power consumption and fast access time relative to a dynamic random access memory (DRAM) device. An SRAM cell comprises a latch and one or more access devices. The latch stores binary data, and the access device provides the capability to read and write data into the latch. Multiple access devices provide multiple access paths to read and write the single latch data.
One advance in the field of SRAM devices has been the development of a dual port SRAM capable of performing a read and write operation at high speeds in place of the conventional single port SRAM. In general, one unit memory cell of a single port SRAM device is composed of six transistors, that is, two load transistors, two drive transistors and two active transistors, to perform the read and write operations sequentially. In contrast, a dual port SRAM device is configured with an addition of two active transistors to the general single port SRAM so as to perform the read and write operations in a dual mode, and which is required to obtain a very high speed operation. However, the dual port SRAM's shortcoming is that the read and write operations interfere with each other to cause a characteristic drop in the semiconductor memory cell since the read and write operations are performed simultaneously.
As discussed in US Application 20050047256, the content of which is incorporated by reference, FIG. 1 shows a prior art dual port SRAM cell composed of two load transistors: TL1 and TL2, two drive transistors: TD1 and TD2 and four active transistors: TA1, TA2, TA3 and TA4. First and second load transistors: TL1 and TL2, and first and second drive transistors: TD1 and TD2, are individually connected to form two inverters. The two inverters are cross coupled to create a latch for storing data. A first active transistor TA1 is connected to a read bit line BLR, and a third active transistor TA3 is connected to a write bit line BLW that is positioned adjacently to the read bit line BLR. As TA1 and TA3 access the same node of the latch 10, both BLR and BLW (12) can read or write data. Transistors TL1, TL2, TD1, TD2, TA1, TA2, TA3 and TA4 are appropriately sized to make the read and write states perform properly. SRAM used for Cache memory typically has multiple read and write ports.
A second active transistor TA2 is connected to a complementary read bit line !BLR, and a fourth active transistor TA4 is connected to a complementary write bit line !BLW that is arranged adjacent to the complementary read bit line !BLR. Further, a read word line WLR is shared with the first active transistor TA1 that is connected to the read bit line BLR, and with the second active transistor TA2 connected to the complementary read bit line !BLR. A write word line WLW is shared with the third active transistor TA3 connected to the write bit line BLW and with the fourth active transistor TA4 connected to the complementary write bit line !BLW. Complementary bit lines and word lines offer higher operating margins for the latch 10. FIG. 2A shows a generic representation of prior art multi-port memory cells. Memory cell in FIG. 2A, includes a storage unit (SU) 20. The SU may or may not be coupled to power Vcc and ground Vss. Access devices 21, 23, 25 and 27 couple one or more nodes of the SU 20 to bit-lines and word-lines as shown. The configurable element in SU 20 may be a latch, Flash element, DRAM element, EPROM element, EEPROM element, or any other property changeable element. FIG. 2B shows the SRAM implementation, while FIG. 2B shows a Flash implementation of SU 20. In FIG. 2B, the memory cells are selected by a plurality of world lines WL1 and WL2 as well as bit lines BL1 and BL2 and their complementary bit lines !BL1 and !BL2 (!BL denotes NOT bit-line). Pass transistors 102 and 106 are controlled by WL2, while pass transistors 112 and 116 are controlled by WL1. Pass transistor 102 is connected between inverter 104 and !BL2, while pass transistor 106 is connected between inverter 104 and BL2. Correspondingly, pass transistor 112 is connected between inverter 114 and !BL1, while pass transistor 116 is connected between inverter 114 and VBL1. In FIG. 2, the inverter may have a PMOS pull-up device (in which case the memory cell is equivalent to FIG. 1), a Resistor-load, or a Thin-Film PMOS transistor. In FIG. 2, one or both inverters 104, 114 may comprise a thin-film inverter. Similarly, one or more transistors 102, 106, 112, 116 may also comprise transistors constructed on a substrate layer, or a thin-film semiconductor layer.
FIG. 2C shows a floating gate (EEPROM) memory cell. In the SU 20, a floating gate 111 is coupled to a write access device 107 via a tunneling diode 109. Access device 107 couples the tunneling node 109 to write word line WLw and write bit line BLw. Orthogonality ensures individual bit access in an array of bits. Charge is injected to floating gate 111 to program or erase the cell: negative charge programs the bit to off state, positive charge erases the bit to on state. A read word line WLr is capacitively coupled to floating gate 111 at by capacitor 117, and a floating gate pass-transistor 115 is coupled between read bit line pair BLr1 and BLr2. Thus activating WLr enables to read the state of bit thru BLr pair: a conductive state and a no-conductive state. Typical EEPROM's have a single write port and a single read port. Transistor sizing and material thicknesses are carefully balanced to write data during write mode and not to disturb the floating gate during a read mode.